1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device, and more particularly, to a stack package that may implement conductive supports.
2. Description of the Related Art
The electronic industry may seek methods, techniques and designs to produce electronic products that may be (for example)smaller, lighter, faster, more efficient, operate at higher speeds, provide multiple functions and/or result in improved performance, at an effective cost. One method that has been implemented is a chip scale packaging technique. The chip scale packaging technique may provide chip scale packages or chip size packages (CSPs).
To increase the capacity of semiconductor chips and/or decrease package size, cells may be arranged more densely in a limited area of the semiconductor chip. One approach has been 3-D type semiconductor packaging technologies that may involve stacking semiconductor chips and/or semiconductor packages.
A 3-D stack chip packaging technique may involve stacking semiconductor chips. Such chip stacking may, however, negatively impact production rates. For example, a single faulty chip in a stack of semiconductor chips may cause the whole stack of semiconductor chips to be faulty and/or non-repairable. Typically, chips may not be validated until after they have been packaged.
Another 3-D stack chip packaging technique may involve stacking packages instead of chips. Although a stack of packages may be thicker than a stack of chips (e.g., because each chip may include its own package), each package may be individually validated before stacking.
A conventional stack package 100 implementing a board on chip (BOC) package is described with reference to FIG. 1.
Referring to FIG. 1, the stack package 100 may have two unit packages 10 inclusive of an upper unit package 10a and a lower unit package 10b. 
Each unit package 10 may include a substrate 20 having a top surface supporting a semiconductor chip 30, and a bottom surface supporting conductive bumps 60. The substrate 20 may have a window 25, and the semiconductor chip 30 may have pads 31 exposed through the window 25. Bonding wires 40 may connect the pads 31 to the substrate 20 through the window 25. An encapsulant 50 may seal the pads 31 and the bonding wires 40. The conductive bumps 60, which may serve as external connection terminals, may be arranged on the bottom surface of the substrate 20.
In the package structure, the semiconductor chip 30 may be exposed to the external environment. The conductive bumps 60 may have a greater height than the encapsulant 50 so that the unit package 10 may be attached to a motherboard and/or another unit package, for example.
The stack package 100 may be assembled by connecting the upper unit package 10b to the lower unit package 10a by the conductive bumps 60. For example, a flux may be applied to the conductive bumps 60 of the upper unit package 10b. The conductive bumps 60 of the upper unit package 10b may be mounted on the lower unit package 10a and melted.
The encapsulant 50 of the upper unit package 10b may be close to the semiconductor chip 30 of the lower unit package 10a. 
A substrate may be larger than a semiconductor chip. When the semiconductor package is mounted on external equipment, it may occupy a large mounting area.
Further, the semiconductor chip and the substrate may have different coefficients of thermal expansion. If thermal stresses are applied to a package, the package may warp, and conductive bump joint faults may be experienced.
The semiconductor chip 30 may be exposed to the external environment, and the semiconductor chip 30 may be susceptible to external factors.
An encapsulant may be provided on the top surface of the substrate. This may reduce a top surface area of the substrate that may be available for attachment of conductive bumps. Therefore, the encapsulant may be limited to an area of the top surface between a semiconductor chip mounting area and the conductive bump attaching area. Alternatively (or in addition), a larger substrate may be implemented.
On the one hand, the limited area of the encapsulant may be insufficient to resist the package warpage. On the other hand, the use of the larger substrate may increase the unit package area.
The bottom surface of the substrate corresponding to a chip mounting area may not be used as a conductive bump attaching area. If the number of conductive bumps increases, the use of a larger substrate having a larger conductive bump attaching area may be inevitable.